1. Field of the Invention
The present invention is related to cache memories, and more particularly to systolic network circuit topologies and methods of propagating requests and data within a cache memory having a spiral organization.
2. Description of Related Art
A spiral cache memory as described in the above-incorporated parent U.S. Patent application provides a move-to-front (M2F) network via which values are moved to a front-most storage tile, where the access time at an interface to a processor or a lower-order level of a memory hierarchy are shorter than an average value of access times for all of the tiles in the spiral, and a push-back network that moves values backwards to make room for new values moved, at their time of access, to the front-most storage tile. The push-back and M2F networks also couple the spiral cache to a backing store, so that requests that miss in the spiral cache can be loaded into the front-most tile of the spiral cache via the M2F network and values for which no more storage is available can be ejected to the backing store via the push-back network. As described in the above-incorporated parent U.S. Patent Application, the M2F and push-back networks operate according to a systolic pulse, which can be used advantageously to pipeline requests and data while not requiring buffering within the spiral cache itself.
Therefore, it would be desirable to provide an efficient network topology and methodology for providing systolic networks within a spiral cache.